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a 400 msps 14-bit, 1.8v cmos direct digital synthesizer preliminary technical data AD9954 rev. prb information furnished by analog dev i ces is believ ed to be accurate and reliable. how e v e r, no responsibility is assumed by analog dev i ces for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherw i se under any patent or patent rights of analog dev i ces. trademarks and registered trademarks are the property of their respectiv e companies. one technol ogy way , p. o. box 9106, nor w ood, m a 02062-9106, u. s. a . tel : 781/ 329-4700 www.anal og.com fax: 781/326-8703 ? 2002 a n alog dev i ces, inc. a ll rights reserv e d. features 400 msps internal clock speed in teg r ated 14-b i t d/a co n v erter pro g r ammab l e p h ase/amp litu d e d i th erin g 3 2 - bit tuning word ph ase no ise < = - 125 d b c/hz @ 1khz o ffset (da c o u t p u t) excellen t dy n a mic perfo rman ce 80d b sf dr @ 130mhz (+ /- 100khz offset) a o u t serial i/o control ultra-h i g h sp eed an alo g co mp arato r , < 1 p s rms jitter a u toma tic line a r a nd non-line a r fre que nc y sw e e p ing capability 4 f r eq u e n c y / ph ase offset pro f iles 1 . 8 v pow e r supply softw a r e a nd ha rdw a re c ontrolle d pow e r dow n 48-lead epa d-t q f p p ackag e line a r a nd non-line a r fre que nc y s w e e p ing c a p a b ility in teg r ated 1024x32 w o rd ra m support for 5 v input le v e ls on mos t digita l inputs pll refclk multiplier (4x to 20x) internal oscillator, can be driv en by a single cry s tal phase modulation capability multi-chip synchronization applications a g ile l.o. frequency sy nthesis progra mma ble cloc k ge ne ra tor fm chirp sourc e for ra da r a nd sc a nning sy s t e m s a u tomotiv e radar t est an d measu remen t eq u i p m en t a c ous to-optic de v i c e driv e r functional block diagram da c dac i- se t aou t aou t s y s t em c l oc k ti m i ng & cont rol l ogi c i/ o upd a te refcl k sy nc out c o m p ar at or io po rt c o n t r o l re gi st er s sy n c re set m u x 4x -2 0x cl oc k mu ltip le r s y s t em c l oc k refclk os cil lato r /b uff e r sy nc 0 4 m u x ph as e ac cu m u l a t o r cos ( x ) ph as e of f s et dds cor e 19 z -1 z -1 dd s cl o c k ps < 1 : 0 > os k pw rdw n s t a t ic r a m 10 24 x 3 2 32 10 3 32 ra m da t a m u x 14 m u x ra m da t a < 3 1 : 1 8 > f r e que nc y a ccu m u la t o r 32 32 32 32 14 32 an al og in + _ cl ock ou t cry s tal out ena b l e 14 p h a s e a cc umul a t o r r e s e t f r equen cy tunin g w o r d dd s c l o ck ra m c o n t r o l r a m a ddr ram d a t a de l t a f r e q . ra m p ra t e d e l t a f r e q . tu ni ng w o r d ,
preliminary technical data AD9954 rev. prb 1/29/03 page 2 analog devices, inc. general description the AD9954 is a direct digital synthesizer (dds) featuring a 14-bit dac operating up to 400msps. the AD9954 uses advanced dds technology, coupled with an internal high-speed, high performance d/a converter to form a digitally- programmable, complete high-fre quency synthesizer capable of generating a frequency-agile anal og output sinusoidal waveform at up to 200 mhz. the AD9954 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). the frequency tuning and control words are loaded into the AD9954 via a serial i/o port. the AD9954 includes an integrated 1024x32 static ram to support flexible frequency sweep capability in several modes. the AD9954 also supports a user defined linear sweep mode of operation. the device includes an on-chip high speed comparator for applications requiring a square wave output. the AD9954 is specified to operate over the extended industrial temperature range of -40 to +85c. absolute maximum ratings 1 maximum junction temp. ............................. +150 c storage temperatu re ................................... -65 c to +1 50 c vs ............................................................................ +4 v operating temp. ........................... ................. -40 c to +85 c digital input voltage ............................... -0.7 v to +vs lead temp. ( 10 sec. soldering) ............................. ...... +300 c digital output current ....................................... 5 ma t ja .................................................................................. 38c/w t jc 15 c/w * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. contents functional block diagram 1 general description 2 AD9954 preliminary electrical specifications 5 AD9954 pinmap 8 pin name 9 i/o 9 theory of operation 11 component blocks 11 dds core 11 phase truncation 12 clock input 12 phase locked loop (pll) 13 dac output 13 comparator 14 serial io port 14 register maps and descriptions 14 control register bit descriptions 18 control function register #1 (cfr1) 18 control function register #1 (cfr2) 25 other register descriptions 26 amplitude scale factor (asf) 26 amplitude ramp rate (arr) 26
preliminary technical data AD9954 frequency tuning word 0 (ftw0) 26 phase offset word (pow) 26 frequency tuning word 1 (ftw1) 27 negative & positive linear sweep control word (nlscw), (plscw) 27 ram segm ent control words 0,1,2,3 (rscw0) (rscw1) (rscw2), (rscw3) 27 ram 27 linear sweep block 28 modes of operation 28 single tone mode 28 ram controlled modes of operation 28 direct switch mode 28 ram p -up mode 29 bi-directional ram p mode 30 continuous bi-directional ram p mode 31 continuous re-circulate mode 31 ram controlled modes of operation sum m a ry 32 internal profile control 33 linear sweep mode 34 linear sweep no dwell feature 35 program m i ng the ram p rate tim er 38 continuous and ?clear and release? fr equency and phase accum u lator clear functions 38 continuous clear bits 38 clear and release function 39 program m i ng AD9954 features 39 phase offset control 39 phase/am plitude dithering 39 shaped on-off keying 40 auto shaped on-off keying m ode operation: 42 osk ramp rate timer 42 external shaped on-off keying m ode operation: 43 synchronization; register updates (i/o update) 43 functionality of the syncclk and i/o update 43 figure d- i/o synchroni zation block diagram 44 figure e - i/o synchroni zation tim i ng diagram 44 synchronizing multiple AD9954s 45 using a single crystal to driv e multiple AD9954 clock inputs 45 serial port operation 46 instruction byte 47 serial interface port pin description 48 msb/lsb transqfers 48 example operation 49 ram i/o via serial port 49 notes on serial port operation 50 power down functions of the AD9954 50 rev . p r b 1/29/03 page 3 analog devices , inc.
preliminary technical data AD9954 digital and input clock power down error! bookmark not defined. AD9954 application suggestions 52 rev . p r b 1/29/03 page 4 analog devices , inc.
preliminary technical data AD9954 rev. prb 1/29/03 page 5 analog devices, inc. AD9954 preliminary electrical specifications (unless otherwise noted: (v s =+1.8 v r 5%, r set =1.96 k : , external reference clock frequency = 20 mhz with refclk multiplier enabled at 20 u ) parameter temp test level AD9954 min typ max units ref clock input characteristics frequency range refclk multiplier disabled full vi 1 400 mhz refclk multiplier enabled at 4x full vi 20 100 mhz refclk multiplier enabled at 20x full vi 4 20 mhz input capacitance +25c v 3 pf input impedance +25c v 100 m : duty cycle +25c v 50 % duty cycle with refclk multiplier enabled +25c v 35 65 % dac output characteristics resolution 14 bits full scale output current +25c 5 10 15 ma gain error +25c i -10 +10 %fs output offset +25c i 0.6 p a differential nonlinearity +25c v 1 lsb integral nonlinearity +25c v 2 lsb output capacitance +25c v 5 pf residual phase noise @ 1 khz offset, 40 mhz a out refclk multiplier enabled @ 20 u +25c v -89 dbc/hz refclk multiplier enabled @ 4 u +25c v -105 dbc/hz refclk multiplier disabled +25c v -116 dbc/hz voltage compliance range +25c i avdd- 0.375 avdd + 0.25v v wideband sfdr: 1 ? 20 mhz analog out +25c v dbc 20 ? 40 mhz analog out +25c v dbc 40 ? 60 mhz analog out +25c v dbc 60 ? 80 mhz analog out +25c v dbc 80 ? 100 mhz analog out +25c v dbc 100 ? 120 mhz analog out +25c v dbc 120 ? 140 mhz analog out +25c v dbc 140 ? 160 mhz analog out +25c v dbc narrow band sfdr 10 mhz analog out (1 mhz) +25c v dbc 10 mhz analog out (250 khz) +25c v dbc 10 mhz analog out ( 50 khz) +25c v dbc 10 mhz analog out ( 10 khz) +25c v dbc 65 mhz analog out ( 1 mhz) +25c v dbc 65 mhz analog out ( 250 khz) +25c v dbc 65 mhz analog out ( 50 khz) +25c v dbc 65 mhz analog out ( 10 khz) +25c v dbc 80 mhz analog out ( 1 mhz) +25c v dbc 80 mhz analog out ( 250 khz) +25c v dbc 80 mhz analog out ( 50 khz) +25c v dbc 80 mhz analog out ( 10 khz) +25c v dbc 100 mhz analog out ( 1 mhz) +25c v dbc 100 mhz analog out ( 250 khz) +25c v dbc 100 mhz analog out ( 50 khz) +25c v dbc 100 mhz analog out ( 10 khz) +25c v dbc 120 mhz analog out ( 1 mhz) +25c v dbc 120 mhz analog out ( 250 khz) +25c v dbc 120 mhz analog out ( 50 khz) +25c v dbc 120 mhz analog out ( 10 khz) +25c v dbc 140 mhz analog out ( 1 mhz) +25c v dbc 140 mhz analog out ( 250 khz) +25c v dbc 140 mhz analog out ( 50 khz) +25c v dbc 140 mhz analog out ( 10 khz) +25c v dbc 160 mhz analog out ( 1 mhz) +25c v dbc 160 mhz analog out ( 250 khz) +25c v dbc
preliminary technical data AD9954 p a r a m e t e r t e m p tes t min typ m a x un its l e v e l 160 mhz analog out ( 50 khz) +25c v dbc 160mhz analog out ( 10 khz) +25c v dbc comparator input characteristics i nput capacitance +25 c v 3 pf i nput resistance +25 c i v 500 k ? i nput cur r e nt +25 c i 12 a hy ster esis +25 c i v 30 45 m v comparator output characteristics l ogic ?1? voltage, high z load ful l vi +1. 6 v l ogic ?0? voltage, high z load ful l vi +0. 4 v pr opagation delay +25 c i v 3 ns output duty cycle error 3 + 2 5 c i v 5 % rise/fall t i m e , 5pf load +25 c i v 1 ns t oggle rate, high z load +25 c i v m h z output jitter 4 + 2 5 c i v 1 p s rm s comparator narrowband sfdr 2 10m hz ( 1 m h z) 10m hz ( 250khz) 10m hz ( 50khz) 10m hz ( 10khz) 70m hz ( 1 m h z) 70m hz ( 250khz) 70m hz ( 50khz) 70m hz ( 10khz) 110m hz ( 1 m h z) 110m hz ( 250khz) 110m hz ( 50khz) 110m hz ( 10khz) 140m hz ( 1 m h z) 140m hz ( 250khz) 140m hz ( 50khz) 140m hz ( 10khz) 160m hz ( 1 m h z) 160m hz ( 250khz) 160m hz ( 50khz) 160m hz ( 10khz) +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c +25 c v v v v v v v v v v v v v v v v v v v v 80 85 90 95 80 85 90 95 80 85 90 95 80 85 90 95 80 85 90 95 dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc clo c k g e nerato r o u tput jitter 3 5 m h z a out 10 m h z a out 40 m h z a out 80 m h z a out 120 m h z a out 140 m h z a out 160 m h z a out +25 c +25 c +25 c +25 c +25 c +25 c +25 c v v v v v v v 20 20 20 20 20 20 20 ps rm s ps rm s ps rm s ps rm s ps rm s ps rm s ps rm s timing characteristics serial co n t ro l bu s m a xim u m fr equency m i nim u m clock pulse w i dth l o w ( t pwl ) m i nim u m clock pulse w i dth high ( t pwh ) m a xim u m clock rise/fall t i m e m i n i mu m d a t a s e t u p t i me ( t ds ) m i n i mu m d a t a h o l d t i me ( t dh ) m a x i mu m d a t a v a l i d t i me ( t dv ) w a ke- u p t i m e 4 minim u m reset pulsewidth high (t rh ) full full full full full full full full full full iv iv iv iv iv iv iv iv iv iv 7 7 10 0 25 5 5 1 25 mhz ns ns ns ns ns ns ms sysclk cycles 5 cm os l ogi c i n put s logic ? 1 ? voltage @ dvdd = 1.8v logic ? 0 ? voltage @ dvdd = 1.8v logic ? 1 ? voltage @ dvdd = 3.3v logic ? 0 ? voltage @ dvdd = 3.3v l ogic ?1? cur r e nt l ogic ?0? cur r e nt i nput capacitance +25 c +25 c +25 c +25 c +25 c +25 c +25 c i i i i v 1. 25 2. 2 3 0. 6 0. 8 12 12 v v v v a a pf cm os l ogi c out p ut s (1m a load) dvdd=1.8v l ogic ?1? voltage l ogic ?0? voltage +25 c +25 c i i 1. 35 0. 4 v v rev . p r b 1/29/03 page 6 analog devices , inc.
preliminary technical data AD9954 p a r a m e t e r t e m p tes t min typ m a x un its l e v e l power supply +vs cu rren t full oper ating conditions 400 m h z clock 120 m h z clock power - d own m ode full-sleep mode +25 c +25 c +25 c +25 c +25 c +25 c i i i i i i 30 tbd tbd tbd tbd tbd ma ma ma ma ma ma notes 1 absolute m a xim u m ratings are lim iting values to be applied i ndividually, and be yond which the serviceability of the circuit m a y be im paired. functional operability under any of these conditions is not necessarily im plied. exposure of absolute m a xim u m ratin g co n d itio n s fo r ex ten d e d p e rio d s o f tim e affect d e v i ce reliab ility. 2 com p arator input originates from dds sec tion via external 7-pole elliptic lpf. si ngle-ended input, .5v p-p. com p arator out put t e rm i n at ed i n 50 ohm s . 3 rep r esen ts co m p arato r?s in h e ren t cycle-to -cycle j itter co n t rib u tio n . 4 w a ke-up ti m e refers t o recovery from anal og power down m ode s (see power down m odes of operat i on). the l ongest t i m e req u i red is fo r th e referen ce clo c k mu ltip lier pll to lo ck u p (if it is b e in g u s ed ). th e w a k e -up tim e assu m e s th at th ere is n o capacitor on dac_bp, and that the recom m e nded pll loop filter values are used. 5 sysclk refers to the actual clock freque ncy used on-chip by the AD9954. if the reference clock multiplier is used to m u ltip ly th e ex tern al referen ce freq u e n c y, th en th e sysclk freq u e n c y is th e ex tern al freq u e n c y m u ltip lied b y th e referen ce clo c k mu ltip lier m u ltip licatio n facto r . if th e referen ce clo c k mu ltip lier is n o t u s ed , th en th e sysclk freq u e n c y is th e sam e as the external refclk frequency. ex planation of test levels i ? 100% product i on test ed. ii ? 100% product i on test ed at +25 c and sam p le tested at specified tem p eratures. iii ? sam p le tested only . iv ? param e t e r i s guarant eed by desi gn and charact eri zat i on t e st i ng. v ? param e t e r i s a t y pi cal val u e onl y . vi ? devi ces are 100% product i on t e st ed at +25c and guara nt eed by desi gn and charact eri zat i on t e st i ng for i ndust r i a l operat i ng t e m p erat ure range. ordering guide model temperature range package description package option AD9954asv -40c t o +85c 48-l ead qfp epad sv-48 AD9954pc b + 2 5 c eval uat i o n b o a r d caution esd (electrostatic discharge) s ensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge w i thout detection. although the AD9954 f eatures proprietary esd protection circuitry , permanent damage may occur on devices subjected to high-energy electrostatic discharges. t herefore, proper esd prec autions are recommended to avoid performance degradation or loss of functionality . rev . p r b 1/29/03 page 7 analog devices , inc.
preliminary technical data AD9954 AD9954 pinmap avd d os c/ r e f c l k os cb / r e f c l kb ag n d a d 9954 pi nout 48 leads 35 34 33 32 31 30 29 27 26 25 23 22 21 20 18 17 16 15 14 12 11 10 13 47 46 45 44 43 42 41 40 39 48 11 36 38 37 28 24 19 9 8 7 6 5 4 3 2 1 d a c b p d a c _ r s e t s y n c c l k dv dd i/o u p d a te d g n d p s 1 o s k s c l k _ c s res e t s d i o d v d d _ i o dgnd s d o i o s y n c lo o p _f i l t e r dgnd dv dd p s 0 pw r d w n c t l a g n d a v d d a v d d a g n d i o u t b i o u t a g n d a v d d c l km odes e l e ct cr y s t a l ou t com p _ i n com p _ i nb com p _ o ut avd d ag n d ag n d s y n c i n a g n d a v d d ag n d avd d avd d avd d figure 1 AD9954 pinmap rev . p r b 1/29/03 page 8 analog devices , inc.
preliminary technical data AD9954 hardw a re pin descriptions pin # pin name i/o description 1 i/o update i the rising edge transfers the contents of the internal buffer m e m o ry to the io registers. 2,34 dvdd i digital power supply pins. 3,33, 42 dgnd i digital power ground pins. 4,6, 13,16, 18,19, 25,27, 29 avdd i analog power supply pins. 5,7, 14,15, 17,22, 26,32 agnd i analog power ground pins. 8 oscb/refclkb i com p lem e ntary reference clock/oscillator input (400mhz m a x.). note: w h en the refclk port is operated in single-ended m ode, then refclkb should be decoupled to avdd with a 0.1 f capacitor. 9 osc/refclk i reference clock/oscillator input (400 mhz m a x.). see clock input section of datasheet for details on the refclk/oscillator operation. 10 crystal out o output of the oscillator section. 11 clkmodeselect i control pin for the oscillator section. w h en high, the oscillator section is enabled. w h en low, the oscillator section is bypassed. 12 loop_filter i this pin provides the connection for the external zero com p ensation network of the refclk multiplier?s pll loop filter. the network consists of a 1k ohm resistor in series with a 0.1 f capacitor tied to avdd. 20 ioutb o com p lem e ntary dac output. 2 1 i o u t o d a c o u t p u t . 23 dacbp i dac ?biasline? decoupling pin. 2 4 d a c _ r s e t i a resistor (3.85k ? nom inal) connected from agnd to dac_rset establishes the ref e rence current f o r the dac. 2 8 c o m p _ o u t o com p arator o u t p u t 3 0 c o m p _ i n i com p a r a t o r i n p u t 31 comp_inb i com p arator com p lem e ntary input 35 pwrdwnctl i input pin used as an external power down control. see the external power down control section of this docum ent for details. rev . p r b 1/29/03 page 9 analog devices , inc.
preliminary technical data AD9954 rev . p r b 1/29/03 page 10 analog devices , inc. 36 reset i active high hardware reset pin. assertion of the reset pin forces the AD9954 to the initial state, as described in the io port register map. 37 iosync i asynchronous active high reset of the serial port controller. when high, the current io operation is immediately terminated enabling a new io operation to commence once iosync is returned low 38 sdo o when operating the i/o port as a 3-wire serial port this pin serves as the serial data output. when operated as a 2-wire serial port this pin is the unused and can be left unconnected. 39 cs-bar i this pin functions as an active low chip select that allows multiple devices to share the io bus. 40 sclk i this pin functions as the serial data clock for io operations 41 sdio i/o when operating the i/o port as a 3-wire serial port this pin serves as the serial data input , only. when operated as a 2-wire serial port this pin is the bi- directional serial data pin. 43 dvdd_i/o i digital power supply (for io cells only, 3.3v optional) 44 sync_in i input signal used to synchronize multiple AD9954s. this input is connected to the sync_clk output of a different AD9954. 45 sync_clk o clock output pin, which serv es as a synchronizer for external hardware. 46 osk i input pin used to control the direction of the shaped on-off keying function when programmed for operation. osk is synchronous to the sync_clk pin. when osk is not programmed, this pin should be tied to dgnd. 47,48 ps0, ps1 i input pins used to select one of the four internal profiles. profile<1:0>are synchronous to the sync_clk pin. any change in these inputs transfers the contents of the internal buffer memory to the io registers (sends an internal i/o update). table 1 hardware pin descriptions
preliminary technical data AD9954 rev . p r b 1/29/03 page 11 analog devices , inc. theory of operation component blocks dds core the output frequency (f o ) of the dds is a function of the frequency of system clock ( sysclk), the value of the frequency tuning word (ftw ), and the capacity of the accumulator (2 32 , in this case). the exact relationship is given below with f s defined as the frequency of sysclk. f o = (ftw)(f s ) / 2 32 { 0 d ftw d 2 31 f o = f s* ( 1 ? ( ftw / 2 32 ) ) { 2 31 < ftw < 2 32 -1 the AD9954 frequency tuning word(s) are unsi gned numbers, where 80000000( hex) represents the highest output frequency possible, commonly re ferred to as the nyquist frequency. values ranging from than 80000001(hex) to ffffffff (hex) w ill be expressed as aliased frequencies less than nyquist. an example using a 3-bit phase ac cumulator will illustrate this principle. for a tuning word of 001, the phase accumulator output (p ao) increments from all zeros to all ones and repeats when the accumulator overfl ows after clock cycle number 8. for the tuning word of 111, the phase accumulator output (pao) decrements fro m all ones to all zeros and repeats when the accumulator overflows after clock cycle number 8. while the phase accumulator outputs are ?reversed? with respect to clock cycles, the outputs provide identical inputs to the phase to amplitude converter, which means the dds output frequencies are identical. mathematically, for a 3-bit accumulator, the following equations apply: f o = f s* (ftw / 2 3 ) { 0 d ftw d 2 2 f o = f s* ( 1 ? ( ftw / 2 3 ) ) { 2 2 < ftw < 2 3 -1 for the 001 frequency tuning word: fout = fs * 1/2 3 = 1/8*fs and for the 111 frequency tuning word: fout = fs * (1 ? 7/8) = 1/8*fs the value at the output of the phase accumulator is translated to an amplitude value via the cos(x) functional block and routed to the dac.
preliminary technical data AD9954 rev . p r b 1/29/03 page 12 analog devices , inc. in certain applications it is desirable to force the output signal to zero phase. simply setting the ftw to 0 does not accomplish this. it only results in the dds core holding its current phase value. thus, a control bit is required to for ce the phase accumulator output to zero. at power up the clear phase accumulator bit is set to logic one but the buffe r memory for this bit is cleared (logic zero). therefore, upon power up, the phase accumulator will remain clear until the first i/o update is issued. phase truncation the 32-bit phase values generated by the phase accu mulator are truncated to 19 bits prior to the cos(x) block. that is, the 19 most significant bits of phase are retained for subsequent processing. this is typical of standard dds architecture and is a trade off between hardware complexity and spurious performance. it can be shown that 19-bit phase resolution is sufficient to yield 14-bit amplitude resolution with an error of less than ? lsb. the decision to truncate at 19 bits of phase guarantees the phase error of the cos(x) block to be less than the phase error associated with the amplitude resolution of the 14-bit dac. clock input the AD9954 supports various clock methodologies. support for differential or single-ended input clocks, enabling of an on-chip oscillator and/or phase-locked loop (pll) multiplier are all controlled via user programmable bits. the ad 9954 may be configured in one of six operating modes to generate the system clock. the mode s are configured using the clkmodeselect pin, cfr2<0>, and cfr2<7:3>. connecting the external pin clkmodeselect to logic high enables the on-chip crystal oscillator circuit. with th e on-chip oscillator enabled, users of the AD9954 connect an external crystal to the refclk and refclkb inputs to produce a low frequency reference clock in the range of 20-30mhz. the signa l generated by the oscillator is buffered before it is delivered to the rest of th e chip. this buffered signal is available via the crystal out pin. bit cfr2<0> can be used to enable or disable the buffer, turning on or off the system clock. the oscillator itself is not powered down in order to avoid long start-up times associated with turning on a crystal oscillator. writing bit cfr2<1> to l ogic high enables the crystal oscillator output buffer. logic low at cfr2<1> disables the oscillator output buffer. connecting clkmodeselect to logic low disables the on-chip oscillator and the oscillator output buffer. with the oscillator disabl ed an external oscillator must provide the refclk and/or refclkb signals. for differential operation these pins are driven with complementary signals. for single-ended operation a 0.1uf capacitor should be connected between the unused pin and the positive power supply. with the capacitor in place th e clock input pin bias voltage is 1.35v. in addition, the pll may be used to multiply the reference frequency by an integer value in the range of the 4 to 20.
preliminary technical data AD9954 rev . p r b 1/29/03 page 13 analog devices , inc. the modes of operation are summarized in the table below. please note the pll multiplier is controlled via the cfr2<7:3> bits, i ndependently of the cfr2<0> bit. clkmodeselect cfr2<0> cfr2<7:3> system clock frequency range (mhz) high low 3 < m < 21 f clk = f osc x m 80 < f clk < 400 high low m < 4 or m > 20 f clk = f osc 20 < f clk < 30 high high x f clk = 0 f clk = 0 low x 3 < m < 21 f clk = f ref x m 80 < f clk < 400 low x m < 4 or m > 20 f clk = f ref 5 < f clk < 400 table 2 clock input modes of operation phase locked loop (pll) the pll is required to facilitate multiplication of the refclk frequency. control of the pll is accomplished by programming the 5-bit refclk mu ltiplier portion of control function register #2, bits <7:3>. when programmed for values ranging from 04h ? 14h (4-20 decimal), the pll multiplies the refclk input frequency by the co rresponding decimal value. th e maximum output frequency of the pll is restricted to 400mhz, however. whenev er the pll value is changed, the user should be aware that time must be allocated to a llow the pll to lock (approximately 1ms). the pll is bypassed by programming a value outsi de the range of 4-20 (decimal). when bypassed, the pll is shut down to conserve power. dac output the AD9954 incorporates an integrated 14-bit current output dac. two complementary outputs provide a combined full-scale output current (i out ). differential outputs reduce the amount of common-mode noise that might be present at the dac output, offering the advantage of an increased signal-to-noise ratio. the full-scale current is controlled by means of an external resistor (r set ) connected between the dac_rset pin a nd the dac ground (agnd_dac). the full-scale current is proportional to the resistor value as follows: r set = 39.19/i out the maximum full-scale output current of the combined dac outputs is 15ma, but limiting the output to 10ma provides the best spurious-fre e-dynamic-range (sfdr) performance. the dac output compliance range is avdd+0.25v to avdd-0.375v. voltages de veloped beyond this range will cause excessive dac distortion and could potentially damage the dac output circuitry. proper attention should be paid to the load termination to keep the output voltage within this compliance range.
preliminary technical data AD9954 rev . p r b 1/29/03 page 14 analog devices , inc. comparator many applications require a square wave signal ra ther than a sine wave. for example, in most clocking applications a high slew rate helps to reduce phase noise and jitter. to support these applications, the AD9954 includes an on-chip compar ator. the comparator has a bandwidth greater than 200mhz and a common mode i nput range of 1.3v to 1.8v. by setting the comparator power- down bit, cfr1<6>, the comparator can be turned off to save on power consumption. serial io port the AD9954 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard micro-controlle rs and microprocessors. the serial i/o port is compatible with most synchronous transfer fo rmats, including both the motorola 6905/11 spi and intel 8051 ssr protocols. the interface allows read/write access to all regist ers that configure the AD9954. msb first or lsb first transfer formats are supported. in add ition, the AD9954?s serial interface port can be configured as a single pin i/o (sdio), which allows a two-wire interface or two unidirectional pins for in/out (sdio/sdo), which enables a three wire interface. two optional pins (iosync and csb) enable greater flexibility for system design-in of the AD9954. register maps and descriptions the register maps are listed in the following tables. the appropriate register map depends on the state of the linear sweep enable bit because certain registers are re-mapped depending on which mode the part is operating in . specifically, registers h?07, h?08, h?09 and h?0a act as the ram segment control words for each of the ram profile slices when the linear sweep enable bit is false. when the linear sweep enable bit is true, h?07 becomes the negative linear sweep control word and h?08 becomes the positive linear sweep control word. the h?09 and h?0a registers are not used in linear sweep mode. because the linear sweep operation takes precedence over ram operations, adi recommends that the ram enable bit cfr1<31> be set to zero when the linear sweep enable bit cfr1<21> is true to cons erve power. the serial address numbers associated with each of the registers are shown in hexadecimal format. angle brackets <> are used to reference specific bits or ranges of b its. for example, <3> designates bit 3 while <7:3> designates the range of bits from 7 down to 3, inclusive. linear sweep enable bit register map false (cfr1<21>=0) ram segment control words active true (cfr1<21> = 1) linear sweep control words active table 3 register mapping based on linear sweep enable bit
preliminary technical data AD9954 rev . p r b 1/29/03 page 15 analog devices , inc. AD9954 register map ? when linear swee p enable bit is false (cfr1<21>=0) (note: ram enable bit cfr1<31> only activates th e ram itself, not the ram segment control words) register name (serial address) bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value or profile <7:0> digital power down comp power down dac power down clock input power dwn external power down mode linear sweep no dwell sync clk out disable not used 00h <15:8> load srr @i/o ud autoclr freq. accum autoclr phase accum enable sine output clear freq accum. clear phase accum. sdio input only lsb first 00h <23:16> automatic sync enable software manual sync linear sweep enable amplitude dither enable phase dither en<3> phase dither en<2> phase dither en<1> phase dither en<0> 00h control function register #1 (cfr1 ) (00h) <31:24> ram enable ram dest. is phase word internal profile control <2:0> load arr @i/o ud osk enable auto osk keying 00h <7:0> refclk multiplier 00h or 01h or 02h or 03h: bypass multiplier 04h ?14h: 4x ? 20x multiplication vco gain charge pump control <1:0> 00h <15:8> not used high speed sync enable hardware manual sync enable crystal out pin active dac prime data disable 00h control function register #2 (cfr2) (01h) <23:16> not used 00h <7:0> amplitude scale factor register <7:0> 00h amplitude scale factor (asf ) (02h) <15:8> auto ramp rate speed control <1:0> amplitude scale factor register <13:8> 00h amplitude ramp rate (arr) (03h) <7:0> amplitude ramp rate register <7:0> 00h <7:0> frequency tuning word #0 <7:0> 00h <15:8> frequency tuni ng word #0 <15:8> 00h <23:16> frequency tuni ng word #0 <23:16> 00h frequency tuning word (ftw0) (04h) <31:24> frequency tuni ng word #0 <31:24> 00h <7:0> phase offset word #0 <7:0> 00h phase offset word (pow0 ) (05h) <15:8> not used<1:0> phase offset word #0 <13:8> 00h
preliminary technical data AD9954 rev . p r b 1/29/03 page 16 analog devices , inc. <7:0> frequency tuning word #1 <7:0> 00h <15:8> frequency tuni ng word #1 <15:8> 00h <23:16> frequency tuni ng word #1 <23:16> 00h frequency tuning word (ftw1) (06h) <31:24> frequency tuni ng word #1 <31:24> 00h <7:0> ram segment 0 mode control <2:0> no dwell active ram segment 0 beginning address <9:6> ps0=0 ps1=0 <15:8> ram segment 0 beginning address <5:0> ram segment 0 final address <9:8> ps0=0 ps1=0 <23:16> ram segment 0 final address <7:0> ps0=0 ps1=0 <31:24> ram segment 0 addre ss ramp rate <15:8> ps0=0 ps1=0 ram segment control word #0 (rscw0 ) (07h) <39:32> ram segment 0 address ramp rate <7:0> ps0=0 ps1=0 <7:0> ram segment 1 mode control <2:0> no dwell active ram segment 1 beginning address <9:6> ps0=1 ps1=0 <15:8> ram segment 1 beginning address <5:0> ram segment 1 final address <9:8> ps0=1 ps1=0 <23:16> ram segment 1 final address <7:0> ps0=1 ps1=0 <31:24> ram segment 1address ramp rate <15:8> ps0=1 ps1=0 ram segment control word #1 (rscw1 ) (08h) <39:32> ram segment 1 address ramp rate <7:0> ps0=1 ps1=0 <7:0> ram segment 2 mode control <2:0> no dwell active ram segment 2 beginning address <9:6> ps0=0 ps1=1 <15:8> ram segment 2 beginning address <5:0> ram segment 2 final address <9:8> ps0=0 ps1=1 <23:16> ram segment 2 final address <7:0> ps0=0 ps1=1 <31:24> ram segment 2 address ra mp rate <15:8> ps0=0 ps1=1 ram segment control word #2 (rscw2 ) (09h) <39:32> ram segment 2 address ramp rate <7:0> ps0=0 ps1=1 <7:0> ram segment 3 mode control <2:0> no dwell active ram segment 3 beginning address <9:6> ps0=1 ps1=1 <15:8> ram segment 3 beginning address <5:0> ram segment 3 final address <9:8> ps0=1 ps1=1 <23:16> ram segment 3 final address <7:0> ps0=1 ps1=1 <31:24> ram segment 3 addre ss ramp rate <15:8> ps0=1 ps1=1 ram segment control word #3 (rscw3 ) (0ah) <39:32> ram segment 3 address ramp rate <7:0> ps0=1 ps1=1 ram (0bh) <31:0> ram [1023:0] <31:0> (read instructions write out ram signature register data) -
preliminary technical data AD9954 rev . p r b 1/29/03 page 17 analog devices , inc. AD9954 register map ? when linear sweep enable bit is true (cfr1<21> = 1) (note: ram enable bit cfr1<31> only activates the ram itself, not the ram segment control words) register name (serial address) bit range (internal address) (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value or profile <7:0> (00h) digital power down comp power down dac power down clock input power dwn external power down mode crystal out pin active sync clk out disable not used 00h <15:8> (01h) load srr @i/o ud autoclr freq. accum autoclr phase accum enable sine output clear freq accum. clear phase accum. sdio input only lsb first 00h <23:16> (02h) automatic sync enable software manual sync linear sweep enable amplitude dither enable phase dither en<3> phase dither en<2> phase dither en<1> phase dither en<0> 00h control function register #1 (cfr1 ) (00h) <31:24> (03h) ram enable ram dest. is phase word internal profile control <2:0> load arr @i/o ud output shaped keying enable auto output shaped keying 00h <7:0> (04h) refclk multiplier 00h or 01h or 02h or 03h: bypass multiplier 04h ?14h: 4x ? 20x multiplication vco gain charge pump control <1:0> 00h <15:8> (05h) currently not used high speed sync enable hardware manual sync enable crystal out pin active dac prime data disable 00h control function register #2 (cfr2) (01h) <23:16> (06h) currently not used 00h <7:0> (07h) amplitude scale factor register <7:0> - amplitude scale factor (asf ) (02h) <15:8> (08h) auto ramp rate speed control <1:0> amplitude scale factor register <13:8> - amplitude ramp rate (arr) (03h) <7:0> (09h) amplitude ramp rate register <7:0> - <7:0> (0ah) frequency tuning word #0 <7:0> 00h <15:8> (0bh) frequency tuning word #0 <15:8> 00h <23:16> (0ch) frequency tuning word #0 <23:16> 00h frequency tuning word (ftw0) (04h) <31:24> (0dh) frequency tuning word #0 <31:24> 00h <7:0> (0eh) phase offset word #0 <7:0> 00h phase offset word (pow0 ) (05h) <15:8> (0fh) open<1:0> phase offset word #0 <13:8> 00h
preliminary technical data AD9954 rev . p r b 1/29/03 page 18 analog devices , inc. <7:0> (10h) frequency tuning word #1 <7:0> - <15:8> (11h) frequency tuning word #1 <15:8> - <23:16> (12h) frequency tuning word #1 <23:16> - frequency tuning word (ftw1) (06h) <31:24> (13h) frequency tuning word #1 <31:24> - <7:0> (14h) falling delta frequency tuning word <7:0> profile0 <15:8> (15h) falling delta frequency tuning word <15:8> profile0 <23:16> (16h) falling delta frequency tuning word <23:16> profile0 <31:24> (17h) falling delta frequency tuning word <31:24> profile0 negative linear sweep control word (nlscw ) (07h) <39:32> (18h) falling sweep ramp rate word <7:0> profile0 <7:0> (19h) rising delta frequency tuning word <7:0> profile1 <15:8> (1ah) rising delta frequency tuning word <15:8> profile1 <23:16> (1bh) rising delta frequency tuning word <23:16> profile1 <31:24> (1ch) rising delta frequency tuning word <31:24> profile1 positive linear sweep control word ( plscw ) (08h) <39:32> (1dh) rising sweep ramp rate word <7:0> profile1 control register bit descriptions control function register #1 (cfr1) the cfr1 is used to control the various func tions, features, and modes of the AD9954. the functionality of each bit is detailed below. cfr1<31>: ram enable bit. when cfr1<31> = 0 (default). when cfr1<31> is inactive, the ram is disabled for operation. either single tone mode of operation or linear sweep mode of operations is enabled. when cfr1<31> = 1, if cfr1<31> is ac tive, the ram is enabled for operation. access control for normal operation is controlled via the mode control bits of the rscw for the current profile.
preliminary technical data AD9954 rev . p r b 1/29/03 page 19 analog devices , inc. cfr1<30>: ram destination bit. cfr1<30> = 0 (default) if cfr1<31> is active, a logic 0 on the ram destination bit (cfr1<30>=0) configures the AD9954 su ch that ram output drives the phase accumulator (i.e. is the frequency tuning word). if cfr1<31> is inactive, cfr1<30> is a don?t care. cfr1<30> = 1 if cfr1<31> is active, a logic 1 on the ram destination bit (cfr1<30>=1) configures the AD9954 such that ram output drives the phase- offset adder (i.e. sets the phase offset of the dds core). cfr1<29:27>: internal profile control bits. these bits cause the profile bits to be ignored and put the AD9954 into an automatic ?profile loop sequence? that allows the user to implement a frequency/phase composite sweep that runs without external inputs. see the internal profile control section of this document for details. cfr1<26>: amplitude ramp rate load control bit. when cfr1<26> = 0 (default) , the amplitude ramp rate timer is loaded only upon timeout (timer ==1) and is not loaded due to an i/o update input signal. when cfr1<26> = 1, the amplitude ramp rate timer is loaded upon timeout (timer ==1) or at the time of an i/o update input signal. cfr1<25>: shaped on-off keying enable bit. when cfr1<25> = 0 (default,) shaped on-off keying is bypassed. when cfr1<25> = 1, shaped on-off ke ying is enabled. when enabled, cfr1<24> controls the mode of operation for this function. cfr1<24>: auto shaped on-off keying enable bit (only valid when cfr1<25> is active high). when cfr1<24> = 0 (default). when cfr1<25> is active, a logic 0 on cfr1<24> enables the manual shaped on -off keying operation. see the shaped on-off keying section of this document for details. when cfr1<24> = 1, if cfr1<25> is ac tive, a logic 1 on cfr1<24> enables the auto shaped on-off keying operation. see the shaped on-off keying section of this document for details.
preliminary technical data AD9954 rev . p r b 1/29/03 page 20 analog devices , inc. cfr1<23>: automatic synchronization enable bit. when cfr1<23> = 0 (default), the automatic synchronization of multiple AD9954s feature is inactive. when cfr1<23> = 1, the automatic sync hronization of multiple AD9954s feature is active. see the synchronizing multiple AD9954s section of this document for details. cfr1<22>: software manual synchronization of multiple AD9954. when cfr1<22> = 0 (default), the manual synchronization of multiple AD9954s feature is inactive. when cfr1<22> = 1, the software cont rolled manual synchronization of multiple AD9954s feature is executed. the sync_c lk rising edge is advanced by one sysclk cycle and this bit is cleared. to advance the rising edge multiple times, this bit needs to be set fo r each advance. see the synchronizing multiple AD9954s section of this document for details. . cfr1<21>: linear frequency sweep enable. when cfr1<21> = 0 (default) , the linear frequency sweep capability of the AD9954 is inactive. when cfr1<21> = 1, the linear freque ncy sweep capability of the AD9954 is enabled. when enabled, either the rising or falling delta freque ncy tuning word is applied to the frequency accumulator at the programmed ramp rate causing the output frequency to ramp up or ramp down, controlled by the profile 0 input. see the linear sweep capability section of this document for details. cfr1<20>: amplitude dither enable bit. when cfr1<20> = 0 (default) , amplitude dithering is disabled. when cfr1<20> = 1, amplitude dithering is enabled.
preliminary technical data AD9954 rev . p r b 1/29/03 page 21 analog devices , inc. cfr1<19>: phase bit <16> dither enable bit. when cfr1<19> = 0 (default) , phase dithering for truncated phase words, bit 16 of <31:13>, is disabled. when cfr1<19> = 1, phase dithering for truncated phase words, bit 16 of <31:13>, is enabled. cfr1<18>: phase bit <15> dither enable bit. when cfr1<18> = 0 (default) , phase dithering for truncated phase words, bit 15 of <31:13>, is disabled. when cfr1<18> = 1, phase dithering for truncated phase words, bit 15 of <31:13>, is enabled. cfr1<17>: phase bit <14> dither enable bit. when cfr1<17> = 0 (default) , phase dithering for truncated phase words, bit 14 of <31:13>, is disabled. when cfr1<17> = 1, phase dithering for truncated phase words, bit 14 of <31:13>, is enabled. cfr1<16>: phase bit <13> dither enable bit. when cfr1<16> = 0 (default) , phase dithering for truncated phase words, bit 13 of <31:13>, is disabled. when cfr1<16> = 1, phase dithering for truncated phase words, bit 13 of <31:13>, is enabled. cfr1<15>: linear sweep ramp ra te load control bit. when cfr1<15> = 0 (default) , the linear sweep ramp rate timer is loaded only upon timeout (timer ==1) and is not loaded due to an i/o update input signal. when cfr1<15> = 1, the linear sweep ramp rate timer is loaded upon timeout (timer ==1) or at the time of an i/o update input signal.
preliminary technical data AD9954 rev . p r b 1/29/03 page 22 analog devices , inc. cfr1<14>: auto clear frequency accumulator bit. when cfr1<14> = 0 ( default ), a new delta frequency word is applied to the input, as in normal operation, but not loaded into the accumulator. when cfr1<14> = 1, this bit automatically synchronously clears (loads zeros into) the frequency accumulator for one cycle upon reception of the i/o update sequence indicator. cfr1<13>: autoclear phase accumulator bit. when cfr1<13> = 0 (default) , a new frequency tuning word is applied to the inputs of the phase accumulator, but not loaded into th e accumulator. when cfr1<13> = 1, this bit automatically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the i/o update sequence indicator. cfr1<12>: sine/cosine select bit. when cfr1<12> = 0 (default) , the angle-to-amplitude conversion logic employs a cosine function. when cfr1<12> = 1, the angle-to-amp litude conversion logic employs a sine function. cfr1<11>: clear frequency accumulator. when cfr1<11> = 0 (default) , the frequency accumulator functions as normal. when cfr1<11> = 1, the frequency accumulator memory elements are asynchronously cleared. cfr1<10>: clear phase accumulator. when cfr1<10> = 0 (default) , the phase accumulator functions as normal. when cfr1<10> = 1, the phase accumula tor memory elements are asynchronously cleared.
preliminary technical data AD9954 rev . p r b 1/29/03 page 23 analog devices , inc. cfr1<9>: sdio input only. when cfr1<9> = 0 ( default ), the sdio pin has bi-directional operation (2-wire serial programming mode). when cfr1<9> = 1, the serial data i/o pin (sdio) is configured as an input only pin (3-wire serial programming mode). cfr1<8>: lsb first. when cfr1<8> = 0 ( default ), msb first format is active. when cfr1<8> = 1, the serial interface a ccepts serial data in lsb first format. cfr1<7>: digital power down bit. when cfr1<7> = 0 ( default ), all digital functions and clocks are active. when cfr1<7> = 1, all non-io digital f unctionality is suspended and all heavily loaded clocks are stopped. this bit is inte nded to lower the digital power to nearly zero, without shutting down the pll cl ock multiplier function or the dac. cfr1<6>: comparator power down bit. when cfr1<6> = 0 ( default ), the comparator is enabled for operation. when cfr1<6> = 1, the comparator is disabl ed and is in its lowest power dissipation state. cfr1<5>: dac power down bit. when cfr1<5> = 0 ( default ), the dac is enabled for operation. when cfr1<5> = 1, the dac is disabled and is in its lowest power dissipation state. cfr1<4>: clock input power down bit. when cfr1<4> = 0 ( default ), the clock input circuitry is enabled for operation. when cfr1<4> = 1, the clock input circuitr y is disabled and the device is in its lowest power dissipation state.
preliminary technical data AD9954 rev . p r b 1/29/03 page 24 analog devices , inc. cfr1<3>: external power down mode. when cfr1<3> = 0 (default) the external power down mode selected is the ?fast recovery power down? mode. in this mode , when the pwrdwnctl input pin is high, the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparator, pll, oscillator, a nd clock input circuitry is not powered down. when cfr1<3> = 1, the external power down mode selected is the ?full power down? mode. in this mode, when the pwrdwn ctl input pin is high, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. cfr1<2>: linear sweep no dwell bit. when cfr1<2> = 0 (default) the linear sweep no dwell function is inactive. when cfr1<2> = 1, the linear sweep no dwell function is active. if cfr1<21>, the linear sweep enable bit, is active and cfr1<2> is active, the linear sweep no dwell function is activated. see the lin ear sweep section of this document for details. if cfr1<21> is clear, this bit is a don?t care. cfr1<1>: syncclk disable bit. when cfr1<1> = 0 (default) , the syncclk pin is active. when cfr1<1> = 1, the syncclk pin assumes a static logic 0 state (disabled). in this state the pin drive logic is shut dow n to keep noise generated by the digital circuitry at a minimum. however, the synchronization circuitry remains active (internally) to maintain normal device timing. cfr1<0>: not used. leave at 0. note: assertion of this bit may cause th e syncclk pin to momentarily stop generating a sync cloc k signal. the device will not be operational during the re-synchronization period.
preliminary technical data AD9954 rev . p r b 1/29/03 page 25 analog devices , inc. control function register #2 (cfr2) the cfr2 is comprised of three bytes located in parallel addresses 06h-04h. the cfr2 is used to control the various functions, fe atures, and modes of the AD9954, primarily related to the analog sections of the chip. all bits of the cfr2 will be routed direc tly to the analog section of the AD9954 as a single 24-bit bus labeled cfr2<23:0>. cfr2<15:12>: not used. cfr2<11>: high speed sync enable bit. when cfr2<11> = 0 (default) the high speed sync enhancement is off. when cfr2<11> = 1, the high speed sync enhancement is on. see the synchronizing multiple AD9954s section of this document for details. cfr2<10>: hardware manual sync enable bit. when cfr2<10> = 0 (default) the hardware manual sync function is off. when cfr2<11> = 1, the hardware manual s ync function is enabled. while this bit is set, a rising edge on the sync_in pi n will cause the device to advance the sync_clk rising edge by one refclk cy cle. unlike the software manual sync enable bit, this bit does not self-clear. once the hardware manual sync mode is enabled, it will stay enabled until this bit is cleared. see the synchronizing multiple AD9954s section of this document for details. cfr2<9>: crystal out enable bit. when cfr2<9> = 0 (default) the crystal out pin is inactive. when cfr2<9> = 1, the crystal out pin is ac tive. when active, the crystal oscillator circuitry output drives the crystal out pin, which can be connected to other devices to produce a reference frequency. cfr2<8>: dac prime data disable bit. when cfr2<8> = 0 ( default ), the dac prime data is enabled for operation. when cfr2<8> = 1, the dac prime data is not generated and these outputs remain logic zeros.
preliminary technical data AD9954 rev . p r b 1/29/03 page 26 analog devices , inc. cfr2<7:3>: reference clock multiplier control bits. see the phase locked loop (pll) section of this document for details. cfr2<2>: vco gain control bit. this bit is us ed to control the gain setting on the vco. cfr<1:0>: charge pump gain control bits. these bits are used to control the gain setting on the charge pum p. other register descriptions amplitude scale factor (asf) the asf register stores the 2-bit auto ramp rate speed value asf<15:14> and the 14-bit am plitude scale factor asf<13:0> used in the output shaped keying (osk) operation. in auto osk operation, that is cfr1<24> = 1, asf < 15:14> tells the osk block how m a ny am plitude steps to take for each increment or decrement. asf<13:0> sets the maximum value achievable by the osk internal multiplier. in manual osk mode , that is cfr1<24>=0, asf<15:14> have no affect. asf <13:0> provide the out put scale factor directly. if the osk enable bit is cleared, cfr1<25>=0, this register ha s no affect on device operation. amplitude ramp rate (arr) the arr register stores the 8-bit am plitude ram p rate used in the auto osk mode, that is cfr1<25>=1, cfr<24>=1. this register program s the rate the am plitude scale factor counter increments or decrements. in the osk is set to manual mode, cfr1<25>=1 cfr<24>=0, or if osk enable is cleared cfr1< 25>=0, this register has no affect on device operation. frequency tuning word 0 (ftw0) the frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the dds core. its specific role is dependent on th e device mode of operation. phase offset word (pow) the phase offset word is a 14-bit register that st ores a phase offset value. this offset value is added to the output of the phase accum ulator to o ffset the current phase of the output signal. the exact value of phase offset is given by the following form ula: ? ? ? ? ? ? = 360 * 2 14 pow when the ram enable bit is set, cfr1<31> = 1, and the ram destination is cleared, cfr1<30>=0, the ram supplies the phase offset wo rd and this register has no affect on device operation.
preliminary technical data AD9954 rev . p r b 1/29/03 page 27 analog devices , inc. frequency tuning word 1 (ftw1) the frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the dds core. its specific role is dependent on the device mode of operation. negative & positive linear sweep control word (nlscw), (plscw) registers h?07 and h?08 are multifunctional regist ers. when the linear sweep bit cfr1<21> is enabled, register h?07 acts as the negative linear sweep control word (nlscw) and register ?h08 acts as the positive linear sweep control wo rd (plscw). each of the linear sweep control words contains a 32-bit delta frequency tuni ng word (fdftw, rdftw) and an 8-bit sweep ramp rate word (fsrrw, rsrrw). the delta fre quency tuning words determine the amount the frequency accumulator will increment or decremen t the resultant tuning word. the sweep ramp rate words determine the rate at which the accumulator will increment or decrement, in number of clock cycles. ram segment control words 0,1,2,3 (rscw0) (rscw1) (rscw2), (rscw3) when the linear sweep enable bit is cleared, cfr1<21> =0, registers h?07, h?08, h?09 and h?0a act as the ram segment control words, rscw0, rscw1, rcsw2 and rcsw3 respectively. each of the ram segment control words contains a 3-bit mode control value, a ?no dwell? bit, a 10-bit beginning address, a 10- bit final address and a 16-bit address ramp rate. please see the section on ram modes of opera tion for details on how each of these values works in the various ram modes of operation. ram the AD9954 incorporates a 1024x32 block of sram. the ram is bi-directional single- port. that is to say, both read and write opera tions from and to the ram are valid, but they cannot occur simultaneously. write operations from the serial i/o port have precedence, and if an attempt to write to ram is made duri ng a read operation, the read operation will be halted. the ram is controlled in multiple ways, dictated by modes of ope ration described in the ram segment control word <7:5> as well as data in the control function register. read/write control for the ram will be descri bed for each mode supported. when the ram enable bit (cfr1<31>) is set, th e ram output optionally drives the input to the phase accumulator or the phase offset adder, depe nding upon the state of the ?ram destination? bit (cfr1<30>). if cfr1<30> is a logic one, th e ram output is connected to the phase offset adder and supplies the phase offset control word(s ) for the device. when cfr1<30> is logic zero (default condition), the ram output is connected to the input of the phase accumulator and supplies the frequency tuning word(s) for the devi ce. when the ram output drives the phase accumulator, the phase offset wo rd (pow, hex address 05h) drives the phase-offset adder. similarly, when the ram output drives the phase offset adder the frequency tuning word (ftw, hex address 04h) drives the phase accumulator. when cfr1<31> is logic zero, the ram is inactive unless being written to via the serial por t. the power up state of the AD9954 is single
preliminary technical data AD9954 rev . p r b 1/29/03 page 28 analog devices , inc. tone mode, in which the ram enable bit is in active. the ram is segmented into four unique slices controlled by the profile<1:0> input pins. all ram writes/reads, unless otherwise specified, are controlled by the profile<1:0> input pins and the respective ram segment control word . the ram can be written to during normal operation but any io operation that commands the ram to be written immediately suspends read operation from the ram, causing the current mode of operation to be non-functional. this excludes single tone mode, as the ram is not read in this mode . linear sweep block linear sweep is a mode of operation whereby ch anges from a start frequency (f0) to a terminal frequency (f1) are not instantaneous but instead ar e accomplished in a sweep or ?ramped? fashion. frequency ramping, whether linear or non-linear necessitates that many intermediate frequencies between f0 and f1 will be output in addition to the primary f0 and f1 frequencies. the linear sweep block is comprised of the fa lling and rising delta frequency tuning words, the falling and rising delta frequency ramp rates a nd the frequency accumulator. the linear sweep enable bit cfr1 <21> enables th e linear sweep block. in add ition, the linear sweep no-dwell bit controls the linear sweep block?s behavior upon reaching the terminal frequency in a sweep. the actual method for programming a frequency swee p is covered in the ?modes of operation? section of this datasheet. modes of operation single tone mode in single tone mode, the dds core uses a single t uning word. whatever value is stored in ftw0 is supplied to the phase accumulator. this value can only be changed static ally, which is done by writing a new value to ftw0 and issuing an i/ o update. phase adjustment is possible through the phase offset register. ram controlled modes of operation direct switch mode direct switch mode enables fsk or psk modulation. the AD9954 is programmed for direct switch mode by writing the ram enable bit tr ue and programming the ram segment mode control bits of each desired profile to logic 000(b ). this mode simply reads the ram contents at the ram segment beginning address for the current profile. no address ramping is enabled in direct switch mode. to perform 4-tone fsk, the user programs each ram segment control word for direct switch mode and a unique beginning address value. in a ddition, the ram enable bit is written true which enables the ram and the ram destination bit is written false, setting the ram output to be the frequency tuning word. the profile<1:0> inputs are th e 4-tone fsk data inputs. when the profile
preliminary technical data AD9954 rev . p r b 1/29/03 page 29 analog devices , inc. is changed, the frequency tuning word stored in the new profile is loaded into the phase accumulator and used to increment the currently stored value in a phase continuous fashion. the phase offset word drives the phase-offset adde r. 2-tone fsk is accomp lished by using only one profile pin for data. programming the AD9954 for psk modulation is simila r to fsk except the ram destination bit is set to a logic 1, enabling the ram output to driv e the phase offset adder. the ftw drives the input to the phase accumulator. toggling the prof ile pins changes (modulates) the current phase value. the upper 14-bits of the ram drive the phase adder (bits <31:18>). bits <17:0> of the ram output are unused when the ram destination b it is set. the ?no dwell? bit is a don?t care in direct switch mode. ramp-up mode ramp-up mode, in conjunction with the segmented ram capability, allows up to four different ?sweep profiles? to be programmed into th e AD9954. the AD9954 is programmed for ramp-up mode by writing the ram enable bit true and pr ogramming the ram mode control bits of each profile to be used to logic 001(b). as in all modes that enable the memory, the ram destination bit controls whether the ram output drives the phase accumulator or the phase offset adder. upon starting a sweep (vian i/o update or change in profile bits), the ram address generator loads the ram segment beginning address bits of the current rscw, driving the ram output from this address and the ramp rate timer lo ads the ram segment address ramp rate bits. when the ramp rate timer finishes a cycle, th e ram address generator increments to the next address, the timer reloads the ramp rate bits and begins a new countdown cycle. this sequence continues until the ram address generator has incremented to an address equal to the ram segment final address bits of the current rscw. if the ?no dwell? bit is clear, when the ram address generator equals the final address, the generator stops incrementing as the terminal fre quency has been reached. the sweep is complete and does not re-start until an i/o update or change in profile is detected to enable another sweep from the beginning to the final ram address as described above. if the ?no dwell? bit is set, when the ram addre ss generator equals the final address, after the next ramp rate timer cycle the phase accumulator is cleared. the phase accumulator remains cleared until another sweep is initiated via an i/o update input or change in profile. notes to the ramp-up mode: 1) the user must insure that the beginning address is lower than the final address. 2) changing profiles automatically terminates the current sweep and starts the next sweep. 3) the AD9954 offers no output si gnal indicating when a terminal frequency has been reached.
preliminary technical data AD9954 rev . p r b 1/29/03 page 30 analog devices , inc. 4) setting the ram destination bit true such that the ram output drives the phase-offset adder is valid. while the above discussion describe s a frequency sweep, a phase sweep operation is also available. another application for ramp-up mode is non- symmetrical fsk modulation. with the ram configured for two segments, using the profile<0 > bit as the data input allows non-symmetrical ramped fsk. bi-directional ramp mode bi-directional ramp mode allows the AD9954 to offer a symmetrical sweep between two frequencies using the profile<0> signal as the c ontrol input. the AD9954 is programmed for bi- directional ramp mode by writing the ram enable bit true and the ram mode control bits of rscw0 to logic 010(b). in bi-directional ramp mode, the profile<1> input is ignored and the profile<0> input is the ramp direction indicator. in this mode, the memory is not segmented and uses only a single beginning and final address. the address registers that affect the control of the ram are located in the rscw a ssociated with profile 0. upon entering this mode (via an i/o upda te or changing profile<0>), the ram address generator loads the ram segment beginning addre ss bits of rscw0 and the ramp rate timer loads the ram segment address ramp rate b its. the ram drives data from the beginning address and the ramp rate timer begins to count down to 1. while operating in this mode, toggling the profile<0> pin does not cause the device to genera te an internal i/o update. that is to say, when the profile<0> pin is acting as the ramp dir ection indicator, any transfer of data from the i/o buffers to the internal registers can only be initiated by a rising edge on the i/o update pin. ram address control now is a function of the prof ile<0> input. when the profile<0> bit is a logic one, the ram address generator increments to the next address when the ramp rate timer completes a cycle (and reloads to start the timer again). as in the ramp-up mode, this sequence continues until the ram address generator has increm ented to an address equal to the final address as long as the profile<0> input remains high . if the profile<0> input goes low, the ram address generator immediately decrements and the ramp rate timer is reloaded. the ram address generator will continue to decrem ent at the ramp rate period until the ram address is equal to the beginning address as long as th e profile<0> input remains low . the sequence of ramping up and down is controlled via the profile<0> input signal for as long as the part is programmed into this mode. the no dwell bit is a ?don?t care? in this mode as is all data in the ram segment control words associated with profiles 1,2,3. only the information in the ram segment control word for profile 0 is used to control the ram in the bi-directional ramp mode. notes to the bi-directional ramp mode:
preliminary technical data AD9954 rev . p r b 1/29/03 page 31 analog devices , inc. 1) the user must insure that the beginning address is lower than the final address. 2) issuing an i/o update automatically termin ates the current sweep causing the starting address to be reloaded and the ramp rate timer to initialize. 3) setting the ram destination bit true such th at the ram output drives the phase-offset adder is valid. while the above discussion describe s a frequency sweep, a phase sweep operation is also available. continuous bi-directional ramp mode continuous bi-directional ramp mode allows the AD9954 to offer an automatic symmetrical sweep between two frequencies. the AD9954 is programmed for continuous bi-directional ramp mode by writing the ram enable bit true and the ra m mode control bits of each profile to be used to logic 011(b). upon entering this mode (via an i/o_update or changing profile<1:0>), the ram address generator loads the ram segment beginning addre ss bits of the current rscw and the ramp rate timer loads the ram segment address ramp rate bits. the ram drives data from the beginning address and the ramp rate timer begins to count down to 1. when the ramp rate timer completes a cycle, the ram address generator increments to the next addre ss, the timer reloads the ramp rate bits and continues counting down. this sequence continues until the ram address generator has incremented to an address equal to the ram segment final address bits of the current rscw. upon reaching this terminal addr ess, the ram address generator will decrement in value at the ramp rate un til it reaches the ram segment beginning address. upon reaching the beginning address, the entire sequence repeats. the entire sequence repeats for as long as the part is programmed for this mode. the no dwell bit is a ?don?t care? in this mode. in general, this mode is identical in control to the bi-directional ramp mode except the ramp up and down is auto matic (no external control via the profile<0> input) and switching profiles is valid. once in this mode, the address generator ramps from beginning address to final address back to beginni ng address at the rate programmed into the ramp rate register. this mode enables generation of an automatic saw tooth sweep characteristic. notes to the continuous bi-directional ramp mode: 1) the user must insure that the beginning address is lower than the final address. 2) changing profiles or issuing an i/o update automatically terminates the current sweep and starts the next sweep. 3) setting the ram destination bit true such th at the ram output drives the phase-offset adder is valid. while the above discussion describes a frequency sweep, a phase sweep operation is also available. continuous re-circulate mode
preliminary technical data AD9954 rev . p r b 1/29/03 page 32 analog devices , inc. continuous re-circulate mode allows the AD9954 to offer an automatic, continuous unidirectional sweep between two frequencies. the AD9954 is programmed for continuous re-circulate mode by writing the ram enable bit true and the ram mode control bits of each profile to be used to logic 100(b). upon entering this mode (vian i/o update or changing profile<1:0>), the ram address generator loads the ram segment beginning addre ss bits of the current rscw and the ramp rate timer loads the ram segment address ramp rate bits. the ram drives data from the beginning address and the ramp rate timer begins to count down to 1. when the ramp rate timer completes a cycle, the ram address generator increments to the next addre ss, the timer reloads the ramp rate bits and continues counting down. this sequence continues until the ram address generator has incremented to an address equal to the ram segment final address bits of the current rscw. upon reaching this terminal addr ess, the ram address generator reloads the ram segment beginning address bits and the sequence repeats. the sequence of circulating through the specified ram addresses repeats for as long as the part is programmed for this mode. the no dwell bit is a don?t care in this mode. notes to the continuous re-circulate mode: 1) the user must insure that the beginning address is lower than the final address. 2) changing profiles or issuing an i/o update automatically terminates the current sweep and starts the next sweep. 3) setting the ram destination bit true such th at the ram output drives the phase-offset adder is valid. while the above discussion describe s a frequency sweep, a phase sweep operation is also available. ram controlled modes of operation summary the AD9954 offers 5 modes of ram controlle d operation, as shown in table 3 below. rscw<7:5> (binary) mode notes 000 direct switch mode no sweeping, profiles valid, no dwell invalid 001 ramp up sweeping, profiles valid, no dwell valid 010 bi-directional ramp sweeping, profile<0> is a direction control bit, no dwell invalid 011 continuous bi- directional ramp sweeping, profiles valid, no dwell invalid 100 continuous re-circulate sweepi ng, profiles valid, no dwell invalid
preliminary technical data AD9954 rev . p r b 1/29/03 page 33 analog devices , inc. 101,110,111 open invalid mode ? default to direct switch table 4 ram modes of operation internal profile control the AD9954 offers a mode in which a composite frequency sweep can be built, for which the timing control is software programmable. the ?i nternal profile control? capability disengages the profile<1:0> pins and enables the AD9954 to take control of switching between profiles. modes are defined that allow continuous or single burst pr ofile switches for three combinations of profile selection bits. these are listed in the table belo w. when the any of the cfr1<29:27> bits are active, the internal profile control mode is engaged. internal profile control is only valid when the device is operating in ram mode. there is no internal profile control for linear sweeping operations. when the internal profile control mode is e ngaged, the ram segment mode control bits are ?don?t care? and the device operates all profiles as if these mode control bits were programmed for ramp-up mode. switching between profiles occu rs when the ram address generator has exhausted the memory contents for the current profile. cfr1<29:27> (binary) mode description 000 internal control inactive 001 internal control active, single burst, activate profile 0, then 1, then stop 010 internal control active, single burst, activate profile 0, then 1, then 2, then stop 011 internal control active, single burst, activate profile 0, then 1, then 2, then 3, then stop 100 internal control active, continuous, activate profile 0, then 1, then loop starting at 0. 101 internal control active, continuous, ac tivate profile 0, then 1, then 2, then loop starting at 0. 110 internal control active, continuous, ac tivate profile 0, then 1, then 2, then 3, then loop starting at 0 111 invalid table 5 internal profile control a single burst mode is one in which the composite sweep is executed once. for example, assume the device is programmed for ramp-up mode a nd the cfr1<29:27> bits are written to 010(b).
preliminary technical data AD9954 rev . p r b 1/29/03 page 34 analog devices , inc. upon receiving an i/o update, the internal contro l logic signals the device to begin executing the ramp-up mode sequence for profile 0. upon reaching the ram segment final address value for profile 0, the device automatically switches to profile 1 and begins executing that ramp-up sequence. upon reaching the ram segment fina l address value for profile 1, the device automatically switches to profile 2 and begins ex ecuting that ramp-up sequence. when the ram segment final address value for profile 2 is reached, the sequence is over and the composite sweep has completed. issuing another i/o update re-starts the burst process. a continuous internal profile control mode is one in which the composite sweep is continuously executed for as long as the device is programmed into that mode. using the example above, except programming the cfr1<29:27> bits to 101(b), the operation would be identical until the ram segment final address value for profile 2 is r eached. at this point, instead of stopping the sequence, it repeats starting with profile 0. linear sweep mode the AD9954 is placed in linear sweep mode by setting the linear sweep enable bit cr1<21>. when in linear sweep mode, th e AD9954 output frequency will ramp up from a starting frequency, programmed by ftw0 to a fi nishing frequency ftw1, or down from ftw1 to ftw0. the delta frequency tuning words and the ramp rate word determine the rate at which this ramping takes place. the linear sweep no-dwell bit cfr1<2> controls the behavior of the device upon reaching the terminal frequency. the 32-b it rising delta frequency tuning word (rdftw) increments the frequency accumula tor is when ramping up from ft w0 to ftw1. the 8-bit rising sweep ramp rate word (rsrrw ) controls the rate at whic h the frequency accumulator is incremented. the 32-bit falling delta freque ncy tuning word (fdftw) decrements the accumulator when ramping down fro m ftw1 to ftw0. the 8-bit fa lling sweep ramp rate word (fsrrw) determines the rate at which the accumu lator is decremented. in linear sweep mode, the different ram profiles are not valid. the profile <0 > pin controls the direction of the sweep, rising to ftw1 or falling to ftw0. upon reaching th e destination frequency, the AD9954 linear sweep function will either hold at the destination frequency until the state on the profile <0> pin is changed or immediately return to the initial freque ncy, ftw0, depending on the state of the linear sweep no-dwell bit cfr1<02>. while operating in linear sweep mode, toggling the profile<0> pin does not cause the device to generate an inte rnal i/o update. that is to say, when the profile<0> pin is acting as the sweep direction indi cator, any transfer of data from the i/o buffers to the internal registers can only be initiated by a rising edge on the i/o update pin. the linear sweep function of the AD9954 requires the lowest frequency to be loaded into ftw0 register and the highest frequency into ftw1 register. for piece-wise, non-linear frequency transitions, it is necessary to reprogram the registers while the frequency transition is in progress to affect the desired response. figure a demonstrat es a typical frequency ramping operation. after a reset or a power-up, the device will initially be in single tone mode. the programming steps to operate in linear sweep mode are: 0) profile inputs at 00
preliminary technical data AD9954 rev . p r b 1/29/03 page 35 analog devices , inc. 1) set the linear sweep enable bit (cfr1<21 >=1) and set or clear the linear sweep no- dwell bit (cfr1<2>={0,1}) as desired. 2) program the rising and falling delta freque ncy tuning words and ram p rate values 3) program the lower and higher output freque ncies into the ftw0 and ftw1 register, respectively. 4) apply an i/o update to move this data in to the registers (the output frequency will be ftw0) 5) change the profile 0 input as desired to sweep between the lower to higher frequency and back. ft w o ft w 1 s i ng l e t o ne l i n e a r s w e e p m o d e p r o f i l e < 0 > = 0 p r o f i l e <0 > = 1 ti m e fo u t p r o f i l e <0 > = 0 a b ? a t point a: load rising ram p ra te registe r , a pply rising dftw; ? a t point b : load falling r a m p r a te r e g i s t er , apply falling dftw. figure a ? linear sw eep frequency plan regarding figure a it can be seen that the devi ce initially powers up in single tone mode. the profile inputs are low which places the ftw0 i nput to the phase accum u lator. the user then configures the device as desired by writing the rising and falling delta fre quency tuning words and ram p rates, as well as the linear sweep enable b it, via the serial port (point a in the figure above). in this example, the linear sweep no-dwell bit is cleared (cfr1<2>=0). linear sweep no dwell feature the linear sweep function can be operated with a ?no dwe ll? feature. if the linear sweep no dwell bit is set, cfr1<2>=1, the rising sweep is st arted in an identical m a nner to the non-no dwell linear sweep m ode. that is, upon detecting a risi ng edge on the profile<0> input pin the rising sweep action is initiated. the frequency continues to sweep up at the rate set by the rising sweep ramp rate at the resolution set by the rising delta frequency tuning word until it reaches the terminal frequency. upon reaching the terminal frequency, the output frequency immediately returns to the
preliminary technical data AD9954 rev . p r b 1/29/03 page 36 analog devices , inc. starting frequency and remains at the starting freque ncy until the device detects a subsequent rising edge on the profile<0> pin. figure b below is an exam ple of the linear sweep m ode operation when the linear sweep no dwell bit is set. th e points labeled a indicate where a rising edge on ps0 is detected and the points labeled b indi cate where the AD9954 has determ ined fout has reached the terminal frequency and automatically re turns to the starting frequency. please note that in this mode each sweep will require a separate ri sing edge on the profile <0> pin. linear sweeps using the no-dwell bit can only be swept from ft w0 to ftw1 using the positive linear sweep control word. toggling the profile <0> from 1 to 0 will not initiate a falling sweep when the no dwell bit is set. ft w 0 ft w 1 fou t ti m e s i ngl e t one m ode li nea r s w eep m ode e nab l ed - no dw e l l bi t s e t bb b a a a figure b ? linear sw eep using no-dw e ll frequency plan general operation of linear sweep capability : in linear sweep m ode the profile 1 pin m u st be tied to logic 0. with linear sweep mode active, when the profile 0 pin transitions from a low to high, the rdftw is applied to the input of the frequency accumulator and the rsrr register is load ed into the sweep rate timer. the sweep rate timer counts down from an initial value to one, at which point the frequency accumulator is allowed to "accumulate" the input. this accumulation of the rdftw at the rate given by the ramp rate (rsrr) continues until the output of the frequenc y adder is equal to the ftw1 register value. at this time, the accumulation is stopped causi ng the AD9954 to output the frequency given by the ftw1. the output rem a ins at ftw1 for as l ong as the profile 0 pin rem a in logic 1.
preliminary technical data AD9954 rev . p r b 1/29/03 page 37 analog devices , inc. when the profile 0 pin transitions from a high to low, the negated fdftw is applied to the input of the frequency accumulator and the fsrr register is loaded into the sweep rate timer. each time the timer counts down to one, the frequency accumula tor is allowed to "accumulate" the input. this accumulation of the negated fdftw at the ra te given by the ramp rate (fsrr) continues until the output of the frequency adder is equal to the ftw0 register value. at this time, the accumulation is stopped causing the AD9954 to out put the frequency given by the ftw0. the output remains at ftw0 for as long as the profile 0 pin remain logic 0.
preliminary technical data AD9954 rev . p r b 1/29/03 page 38 analog devices , inc. programming the ramp rate timer the linear sweep ramp rate timer is a loadable down counter th at, when enabled, continuously counts down from the loaded value to a count of 1. when in a rising transition the loaded value is the rsrrw, when in a falling transition this valu e is the fsrrw. when the ramp rate timer equals 1, the proper rfdtw or fdftw is loaded and the counter begins counting down to one again. this load and count down operation continues for as long as the timer is enabled unless the timer is forced to load before reaching a count of 1. the ramp timer can be loaded before reaching a count of 1 by three methods. method one is by changing the prof ile<0> input pin. when the profile<0> input pin changes from a logic zero to a logic 1, the rsrrw value is load ed into the ramp rate timer, which then proceeds to count down as normal. when the profile<0> input pin changes from a logic one to a logic zero, the fsrr value is loaded into th e ramp rate timer, which then proceeds to count down as normal. the second method in which the sweep ramp rate tim er can be loaded before reaching a count of 1 is if the cfr1<15> bit is set and an i/o update is issued. if sweep is enabled and cfr1<15> is set, the ramp rate timer loads the value dete rmined by the profile<0> pin every time an i/o update is issued. if the profile<0> pin is low (high), the ramp rate timer loads the fsrrw (rsrrw). the last method in which the sweep ramp rate timer can be loaded before reaching a count of 1 is when going from the inactive linear sweep mode to the active linear sweep mode. that is, when the sweep enable bit is being set. the ramp rate that is loaded is a function of the profile<0> input pin. continuous and ?clear and release? freque ncy and phase accumulator clear functions the AD9954 allows for a programmable continuous zeroing of the frequency sweep logic and the phase accumulator as well as a ?clear and release?, or automatic zeroing function. each feature is individually controlled via bits the cfr1. cf r1<14> is the automatic clear frequency accumulator bit and cfr1<13> is the automatic clear phase accumulator bit. the continuous clear bits are located in cfr1<11:10>, where cfr1<11> clears the frequency accumulator and cfr1<10> clears the phase accumulator. continuous clear bits the continuous clear bits are simply static c ontrol signals that, when active high, hold the respective accumulator at zero for th e entire time the bit is active. when the bit goes low, inactive, the respective accumulator is allowed to operate.
preliminary technical data AD9954 rev . p r b 1/29/03 page 39 analog devices , inc. clear and release function the auto clear frequency accumulator bit, wh en set, clears and releases the frequency accumulator upon receiving an i/o update signal or ch ange in one of the profile pins. the auto clear phase accumulator, when set, clears and releases the phase accumulator upon receiving an i/o update or change on one of th e profile pins. the automatic clearing function is repeated for every subsequent i/o update or change on one of the profile pi ns until the appropriate auto- clear control bit is cleared. note: these bits are programmed independently and do not have to be active at the same time. for example, one accumulator may be using the cl ear and release function while the other is continuously cleared. programming AD9954 features phase offset control a 14-bit phase-offset (t ) may be added to the output of the phase accumulator by means of the control registers. this feature provides the user with three different methods of phase control. the first method is a static phase adjustment, where a fixed phase-offset is loaded into the appropriate phase-offset register a nd left unchanged. the result is th at the output signal is offset by a constant angle relative to the nominal signal. th is allows the user to phase align the dds output with some external signal, if necessary. the second method of phase control is where the us er regularly updates the phase-offset register via the i/o port. by properly modifying the pha se-offset as a function of time, the user can implement a phase modulated output signal. ho wever, both the speed of the i/o port and the frequency of sysclk limit the rate at whic h phase modulation can be performed. the third method of phase control involves the ram and the profile input pins. the AD9954 can be configured such that the ram drives the phase ad just circuitry. the user can control the phase offset via the ram in an identical manner allo wed for frequency sweeping. see the ram control and the sweep modes of operation sections for details. phase/amplitude dithering the AD9954 dds core includes optional phase and/ or amplitude dithering controlled via the cfr1<20:16> bits.
preliminary technical data AD9954 rev . p r b 1/29/03 page 40 analog devices , inc. phase dithering is the randomization of the state of the least significant bits of each phase word. phase dithering reduces spurious signal strength caused by phase truncation by spreading the spurious energy over the entire spectrum. the downsid e to dithering is a rise in the noise floor. amplitude dithering is similar, except it a ffects the output signal routed to the dac. the AD9954 uses a 32-bit linear feedback shift re gister (lfsr), shown in figure 7 below, to generate the pseudo random binary sequence that is used for both pha se and amplitude dither data. the lfsr will generate, at the sync_clk rate, the pseudo random sequence only if dithering is enabled. the enable signal is the 4-input or of the dithering control bits (cfr1<20:16>). phase dithering is independently controlled on the four least significant bits of the phase word routed to the angle rotation function. that is, any or all of the phase word four least significant bits may be dithered or not dithered, controlled by th e user via the serial port. specifically, the cfr1<19> bit controls the phase dithering enab le function of the phase word <16> bit. the cfr1<18> bit controls the phase dithering enab le function of the phase word <15> bit. the cfr1<17> bit controls the phase dithering enab le function of the phase word <14> bit. the cfr1<16> bit controls the phase dithering enable function of the phase word <13> bit. this enable function is such that if the bit is high, dithering is enabled. if the bit is low, dithering is not enabled. amplitude dithering uses one control bit to enable or disable dithering. if the amplitude dither enable bit (cfr1<20>) is logic 0, no amplitude dithering is enabled and the data from the dds core is passed unchanged. when high, amplitude dithering is enabled. shaped on-off keying general description: the shaped on-off keying function of the AD9954 allows the user to control the ramp-up and ramp-down time of an ? on-off? emission from the dac. this function is used in ?burst transmissions? of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. auto and manual shaped on-off keying modes ar e supported. the auto mode generates a linear scale factor at a rate determined by the amplitude ramp rate (arr) register controlled by an external pin (osk). manual mode allows the us er to directly control the output amplitude by writing the scale factor value into the amplitude scale factor (asf) register (asf). the shaped on-off keying function may be bypassed (disabled) by clearing the osk enable bit (cfr1<25>=0). the modes are controlled by two bits located in th e most significant byte of the control function register (cfr). cfr1<25> is the shaped on-off keying enable bit. when cfr1<25> is set, the
preliminary technical data AD9954 output scaling function is enable d; cfr1<25> bypasses the function. cfr1<24> is the internal shaped on-off keying active bit. wh en cfr1<24> is set, internal shaped on-off keying m ode is active; cfr1<24> cleared is ex ternal shaped on-off keying mode active. cfr1<24> is a ?don?t care? if the shaped on-off keyi ng enable bit (cfr1<25>) is cleared. the power up condition is shaped on-off keying disabled (cfr1<25> = 0). figure c below shows the block diagram of the osk circuitry. co s(x ) dd s co re to d a c osk en able cfr<25> 0 1 amplit u de scale f a ct or r e gist er (asf ) 0 1 0 0 1 out hold up /dn osk pi n a m plitud e ramp rate registe r (arr ) loa d data en load os k timer cfr1<26> sy nc clo c k clock inc/dec ena b le ra mp rat e time r aut o scale factor ge nerator auto o s k ena b le cfr<24> figure c. on-off shaped keying, block diagram rev . p r b 1/29/03 page 41 analog devices , inc.
preliminary technical data AD9954 auto shaped on-off keying m ode operation: the auto shaped on-off keying mode is active wh en cfr1<25> and cfr1<24> are set. when auto shaped on-off keying m ode is enabled, a si ngle scale factor is internally generated and applied to the multiplier input for scaling the output of the dds core block (see figure 9 above). the scale factor is the output of a 14-bit counter which increm ents/decrem e nts at a rate determ ined by the contents of the 8-bit output ram p rate regist er. the scale factor increases if the osk pin is high, decreases if the pin is low. the scale factor is an unsigned value such that all zeros multiplies the dds core output by 0 (decimal) and 3fffh multiplies the dds core output by 16383 decimal. for those users who use the full am plitude (14-bits ) but need fast ramp rates, the internally generated scale factor step size is controlled vi a the asf<15:14> bits. the table below describes the increment/decrement step size of the internally generated scale factor per the asf<15:14> bits. asf<15:14> (binary) increment/decrement size 0 0 1 0 1 2 1 0 4 1 1 8 table 6 auto-scale factor internal step size a special feature of this mode is that the m a xim u m output am plitude allowed is lim ited by the contents of the am plitude scale factor register. th is allows the user to ra mp to a value less than full scale. osk ram p rate tim e r the osk ram p rate tim er is a loadable down count er, which generates the clock signal to the 14-bit counter that generates the internal scale factor. th e ram p rate tim er is load ed with the value of the asfr every tim e the counter reaches 1 (decim a l). this load and count down operation continues for as long as the tim er is enabled unless the tim er is forced to load before reaching a count of 1. if the load osk tim e r bit (cfr1<26>) is set, the ram p rate tim er is loaded upon an i/o update, change in profile input or upon reaching a value of 1. the ram p tim er can be loaded before reaching a count of 1 by three methods. method one is by changing the osk input pin. when the osk input pin changes state the asfr value is loaded into the ram p rate tim er, wh ich then proceeds to count down as norm a l. the second m e thod in which the sweep ram p rate tim er can be loaded before reaching a count of 1 is if the load osk timer bit (cfr1<26>) bit is set and an i/o update (or change in profile) is issued. rev . p r b 1/29/03 page 42 analog devices , inc.
preliminary technical data AD9954 the last m e thod in which the sweep ram p rate tim er can be loaded before reaching a count of 1 is when going from the inactive auto shaped on-off keying m ode to the active auto shaped on-off keying mode. that is, when the sweep enable bit is being set. external shaped on-off keying m ode operation: the external shaped on-off keying mode is enabled by writing cfr1<25> to a logic 1 and writing cfr1<24> to a logic 0. when configured for external shaped on -off keying, the content of the asfr becomes the scale factor for the da ta path. the scale factors are synchronized to sync_clk via the i/o update functionality. sy nchronization; register updates (i/o update) functionality of the syncclk and i/o update data into the AD9954 is synchronous to the sync _clk signal (supplied externally to the user on the sync_clk pin). the i/o update pin is sam p led on the rising edge of the sync_clk. internally, sysclk is fed to a divide-by-4 fre quency divider to produce the sync_clk signal. the sync_clk signal is provided to the user on th e sync_clk pin. this enables synchronization of external hardware with the device?s intern al clocks. this is accomplished by forcing any external hardware to obtain its tim ing from s ync_clk. the i/o update signal coupled with sync_clk is used to transfer internal buffer conten ts into the control registers of the device. the com b ination of the sync_clk and i/o update pins provides the user with constant latency relative to sysclk and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted. figure e de m onstrates an i/o update tim ing cycle and synchronization. notes to synchronization logic: 1) the i/o update signal is edge detected to generate a single rising edge clock signal that drives the register bank flops. the i/o update signal has no constraints on duty cycle. the minimum low time on i/o up date is one sync_clk clock cycle. 2) the i/o update pin is setup and held ar ound the rising edge of sync_clk and has zero hold tim e and 10ns setup tim e. rev . p r b 1/29/03 page 43 analog devices , inc.
preliminary technical data AD9954 0 1 0 sy nc clk disa ble d q d q d q os k p r ofile<1:0> i/o upda t e e dge detectio n lo gic synccl k gating register me m o ry i/o buff er latches sc lk sdi cs to core logic sy sclk 4 figure d- i/o synchroniz ation block diagram data [1] data[ 1 ] d a t a(2) data (2) d ata(3) dat a ( 3 ) ab sy sc l k sy nclk i/o update data in registe r s data in i/o b u ffers t he device regist ers an i / o u pdate at point a. t h e data is t r an f e rred f r o m the asynch ronously load ed i / o buf fers at p o int b. figure e - i/o synchroniz ation timing diagram rev . p r b 1/29/03 page 44 analog devices , inc.
preliminary technical data AD9954 sy nchronizing multiple AD9954s the AD9954 product allows easy sync hronization of multiple AD9954s. there are three modes of synchronization available to the user: an autom a tic synchronization m ode; a software controlled m a nual synchronization m ode; and a hardware controlled m a nual synchronization m ode. in all cases, when a user wants to synchronize two or m o re devices, the following considerations m u st be observed. first, all units must share a common cl ock source. trace lengths and path im pedance of the clock tree m u st be designed to keep the phase delay of the different clock branches as closely m a tched as possible. second, the i/o update signa l?s rising edge m u st be provided synchronously to all devices in the system . finally, regardless of the internal synchronization m e thod used, the dvdd_i/o supply should be set to 3.3v for all devices that are to be synchronized. avdd and dvdd should be left at 1.8v. in autom a tic synchronization m ode, one device is chosen as a master, the other device(s) will be slaved to this master. when configured in this mode, all the slaves will automatically synchronize their internal clocks to the sync_clk output signal of the m a ster device. to enter autom a tic synchronization m ode, set the slav e device?s autom a tic synchronization bit (cfr1<23>=1). connect the sync_in input(s) to the m a ster sync_clk output. the slave device will continuously update the pha se relationship of its sync_clk until it is in phase with the sync_in input, which is the sync_clk of the m a ster device. when attem p ting to synchronize devices running at sysclk speeds beyond 250msps, th e high-speed sync enhancem ent enable bit should be set (cfr2<11>=1). in software m a nual synchronization m ode, the user forces the device to advance the sync_clk rising edge one sysclk cycle (1/4 sync_clk period). to activate the m a nual synchronization m ode, set the slave device?s soft ware m a nual synchronization bit (cfr1<22> =1). the bit (cfr1<22>) will be immediately cleared. to advance the rising edge of the sync_clk multiple times, this bit will n eed to be set multiple times. in hardware m a nual synchronization m ode, the s ync_in input pin is configured such that it will now advance the rising edge of the sync_clk signal each time the device detects a rising edge on the sync_in pin. to put the device into hardware m a nual synchronization m ode, set the hardware m a nual synchronization bit (cfr2<10>=1 ). unlike the software m a nual synchronization bit, this bit does not self-clear. once the hard ware m a nual synchronization m ode is enabled, all rising edges detected on the sync_in input will caus e the device to advance the rising edge of the sync_clk by one sysclk cycle until this enable bit is cleared (cfr2<10=0). using a single cry s tal to dri ve multiple AD9954 clock inputs the AD9954 crystal oscillator output signal is availa ble on the crystalout pin, enabling one crystal to drive multiple AD9954s. in order to drive mu ltiple AD9954s with one crystal, the crystalout pin of the AD9954 using the external crystal shoul d be connected to the refclk input of the other AD9954. rev . p r b 1/29/03 page 45 analog devices , inc.
preliminary technical data AD9954 the crystalout pin is static until the cfr2<1> bit is set, enabling the output. the drive strength of the crystalout pin is typically very low, so this signal should be buffered prior to using it to drive any loads. serial port operation with the AD9954, the instruction by te specifies read/write operation and register address. serial operations on the AD9954 occur only at the register level, not the byte level. for the AD9954, the serial port controller recognizes the instruction by te register address and autom a tically generates the proper register byte address. in addition, the cont roller expects that all bytes of that register will be accessed. it is a requirement that all bytes of a register be accessed during serial i/o operations, with one exception. the syncio function can be used to abort an io operation thereby allowing less than all bytes to be accessed. there are two phases to a com m unication cycle with the AD9954. phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9954, coincident with the first eight sclk rising edges. the instruction byte provides the AD9954 serial port controller with inform ation regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcom ing data tr ansfer is read or write and the serial address of the register being accessed. [note ? the serial address of the register being accessed is not the same address as the bytes to be written. see th e example operation section below for details]. the first eight sclk rising edges of each com m uni cation cycle are used to write the instruction byte into the AD9954. the rem a ining sclk edges are for phase 2 of the com m unication cycle. phase 2 is the actual data transfer between th e AD9954 and the system controller. the num ber of bytes transferred during phase 2 of the com m unica tion cycle is a function of the register being accessed. for example, when accessing the control f unction register 2, which is three bytes wide, phase 2 requires that three bytes be transferred. if accessing the frequency tuning word, which is four bytes wide, phase 2 requires th at four bytes be transferred. af ter transferring all data bytes per the instruction, the communi cation cycle is completed. at the com p letion of any com m unication cycle, th e AD9954 serial port controller expects the next 8 rising sclk edges to be the instruction byte of the next com m unication cycle. all data input to the AD9954 is registered on the rising edge of sc lk. all data is driven out of the AD9954 on the falling edge of sclk. figures 34 - 37 are useful in understanding the general operation of the AD9954 serial port. rev . p r b 1/29/03 page 46 analog devices , inc.
preliminary technical data AD9954 instruction by te the instruction byte contains the following in form ation as shown in the table below: instruction byte information m s b d 6 d 5 d 4 d 3 d 2 d 1 l s b r / w b x x a 4 a 3 a 2 a 1 a 0 table 7 instruction byte rev . p r b 1/29/03 page 47 analog devices , inc.
preliminary technical data AD9954 r/-wb?bit 7 of the instruction byte determines wh ether a read or write data transfer will occur after the instruction byte write. logic high indicat es read operation. logic zero indicates a write operation. x, x?bits 6 and 5 of the instruction byte are don?t care. a4, a3, a2, a1, a0?bits 4, 3, 2, 1, 0 of the in struction byte determ ine which register is accessed during the data transfer portion of the com m unications cycle. seri al int e rf ace port pi n descri pt i on sclk ? serial clock. the serial clock pin is us ed to synchronize data to and from the AD9954 and to run the internal state machin es. sclk m a xim u m frequency is 25 mhz. csb ? chip select bar. active low input that allo ws m o re than one device on the sam e serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cy cle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio ? serial data i/o. data is always written into the AD9954 on this pin. however, this pin can be used as a bi-directional data line. bit 7 of register address 0h contro ls the configuration of this pin. the default is logic zero, which c onfigures the sdio pin as bi-directional. sdo ? serial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case wher e the AD9954 operates in a single bi-directional i/o m ode, this pin does not output data and is set to a high im pedance state. syncio ? synchronizes the i/o port state m a chines w ithout affecting the addressable registers contents. an active high input on the sync i/o pin causes the current com m unication cycle to abort. after sync i/o returns low (logic 0) another com m unication cycle m a y begin, starting with the instruction byte write. msb/lsb transqfers the AD9954 serial port can support both m o st signifi cant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the control register 00h<8> bit. the default value of control register 00h<8> is low (m sb first). when control register 00h<8> is set high, the AD9954 serial port is in lsb first form at. the instruction byte must be written in the form at indicated by control register 00h<8>. that is, if the AD9954 is in lsb first m ode, the instruction byte must be written from least si gnificant bit to most significant bit. for msb first operation, the serial port controller will generate the most significant byte (of the specified register) address first followed by the ne xt lesser significant byte addresses until the io rev . p r b 1/29/03 page 48 analog devices , inc.
preliminary technical data AD9954 operation is complete. all data written to (read from) the AD9954 must be (will be) in msb first order. if the lsb mode is active, the serial port controller will generate the least significant byte address first followed by the next greater signi ficant byte addresses until the io operation is complete. all data written to (read from) the AD9954 must be (will be) in lsb first order. exampl e operat i on to write the am plitude scale factor register in msb first form at apply an instruction byte of 02h (serial address is 00010(b)). from this instruction, the internal controller w ill generate an internal byte address of 07h (see the register map) for the fi rst data byte written and an internal address of 08h for the next byte written. since the amplitude sc ale factor register is two bytes wide, this ends the communication cycle. to write the am plitude scale factor register in lsb first form at apply an instruction byte of 40h. from this instruction, the intern al controller will generate an internal byte address of 07h (see the register map) for the first data byte written and an internal address of 08h for the next byte written. since the amplitude scale factor register is tw o bytes wide, this ends the com m unication cycle. ram i/o via serial port accessing the ram via the serial port is identical to any other serial io operation except that the num ber of bytes transferred is determ ined by th e address space between the beginning address and the final address as specified in the current ram segment control word (rscw). the final address describes the m o st significant word addr ess for all io transfers and the beginning address specifies the least significant address. ram i/o supports msb/lsb first operation. when in msb first mode, the first data byte will be for the most significant byte of the memory a ddress described by the final address with the rem a ining three bytes m a king up the lesser significant bytes of that address. the rem a ining bytes come in most significant to least significant, de stined for ram addresses generated in descending order until the final four bytes are written into th e address specified as the beginning address. when in lsb first mode, the first data byte will be for the least significant byte of the memory (specified by the beginning address) with th e rem a ining three bytes m a king up the greater significant bytes of that address. the rem a ining bytes come in least significant to most significant, destined for ram addresses generated in ascending order until the final four bytes are written into the m e m o ry address described by the final address. of course, the bit order for all bytes is least significant to most significant firs t when in the lsb first bit is set. when the lsb first bit is cleared (default) the bit order for all bytes is most significant to least significant. the ram uses serial address 01011(b), so the inst ruction byte to write the ram is 0bh, in msb first notation. as m e ntioned above, the ram a ddresses generated are specified by the beginning and final address of the rscw curren tly selected by the profile<1:0> pins. rev . p r b 1/29/03 page 49 analog devices , inc.
preliminary technical data AD9954 n o t e s on seri al port operat i on 1) the AD9954 serial port configuration bits resi de in bits 8 and 9 of cfr1 (address 00h). the configuration changes immediat ely upon writing to this register. for multi-byte transfers, writing to this register m a y occur during the m i ddle of a com m unication cycle. care m u st be taken to compensate for this new confi guration for the rem a inder of the current communication cycle. 2) the system m u st m a intain synchronization with the AD9954 or the internal control logic will not be able to recognize further instruc tions. for example, if the system sends an instruction byte that describes writing a 2-byte register, then pulses the sclk pin for a 3- byte write (24 additional sclk rising edges), co m m unication synchronization is lost. in this case, the first 16 sclk rising edges after the instruction cycle will properly write the first two data bytes into the AD9954, but the next ei ght rising sclk edges are interpreted as the next instruction byte, not the final byte of the previous com m unication cycle. in the case where synchronization is lost between the system and the AD9954, the sync i/o pin provides a means to re-establish synchronizati on without re-initializing the entire chip. the sync i/o pin enables the user to reset the AD9954 state machine to accept the next eight sclk rising edges to be coincident with the instruction phase of a new com m unication cycle. by applying and rem oving a ?high? signal to the sync i/o pin, the AD9954 is set to once again begin perform ing the com m unication cycle in synchronization with the system . any information that had been written to the AD9954 registers during a valid communication cycle prior to loss of synchronization will remain intact. 3) reading profile registers requires that the profile select pins (profile<1:0>) be configured to select the desired register bank. when reading a register that resides in one of the profiles, the register address acts as an offset to select one of the registers am ong the group of registers defined by the profile. while the profile select pins select the appropriate register group. pow e r dow n functions of the AD9954 the AD9954 supports an externally controlled, or hardware, power down feature as well as the m o re com m on software program m a ble power down bits found in previous adi dds products. the software control power down allows the dac , com p arator, pll, input clock circuitry and the digital logic to be individually power down via unique control bits (cfr1<7:4>). with the exception of cfr1<6>, these bits are not active when the externally controlled power down pin (pwrdwnctl) is high. external power down control is supported on the AD9954 via the pwrdwnctl input pin. when the pwrdwnctl i nput pin is high, the AD9954 will enter a power down m ode based on the cfr1<3> bit. when the pw rdwnctl input pin is low, the external power down control is inactive. rev . p r b 1/29/03 page 50 analog devices , inc.
preliminary technical data AD9954 when the cfr1<3> bit is zero, and the pwrdwnctl input pin is high, the AD9954 is put into a ?fast recovery power down? m ode. in this m ode , the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparato r, pll, oscillator, and clock input circuitry is not powered down. the comparator can be powered down by setting the com p arator power down bit, cfr1<6> =1. when the cfr1<3> bit is high, and the pwrdwnc tl input pin is high, the AD9954 is put into the ?full power down? m ode. in this m ode, all func tions are powered down. this includes the dac and pll, which take a significant am ount of tim e to power up. when the pwrdwnctl input pin is high, the i ndividual power down bits (cfr1<7>, <5:4>) are invalid (don?t care) and are unused; however the comparator power down bit, cfr1<6>, will continue to control the power-down of the com p ar ator. when the pwrdwnctl input pin is low, the individual power down bits control th e power down m odes of operation. note ? the power down signals are all designed such that a logic 1 indicates the low power m ode and a logic zero indicates the active, or powered up mode. the table below indicates the logic level for e ach power down bit that drives out of the AD9954 core logic to the analog section and the digital cloc k generation section of the chip for the external power down operation. control mode active description pwrdwnctl = 0 cfr1<3> don?t care software control digital power down = cfr1<7> com p arator power down = cfr1<6> dac power down = cfr1<5> input clock power down = cfr1<4> pwrdwnctl = 1 cfr1<3> = 0 external control, fast recovery power down m ode digital power down = 1?b1; com p arator power down = 1?b0 or cfr1<6>; dac power down = 1?b0; input clock power down = 1?b0; pwrdwnctl = 1 cfr1<3> = 1 external control, full power down m ode digital power down = 1?b1; com p arator power down = 1?b1; dac power down = 1?b1; input clock power down = 1?b1; table 8 power down control functions rev . p r b 1/29/03 page 51 analog devices , inc.
preliminary technical data AD9954 AD9954 application suggestions a d 9954 lpf re fclk r f /if i nput modulated / demodulat ed signal f i gure f sy nt hesized l.o f o r upconv ersion/downconvers i on AD9954 f ilter phase comparator loop filter vc o t u ning word f i gure g digitally programmable ?d iv ide-by -n ? f u nc tion in pll re f s i gnal ad 9954 d d s ad 9954 o n - ch i p c o mp arat or lpf lpf iout tuning word iout f i gure h f r equency agile clock generator cmos l e ve l cl o c k rev . p r b 1/29/03 page 52 analog devices , inc.
preliminary technical data AD9954 rev . p r b 1/29/03 page 53 analog devices , inc. AD9954 d d s lpf i out freque ncy t u ning word crysta l out sy nc out pha s e offset word 1 sa w crystal AD9954 dds lpf i out freque ncy t u ning word sync in pha s e offse t wo rd 2 re f c l k re f c l k refcl k i/i-ba r b a seb and q/q - ba r b a se band rf out figure i tw o a d 9954s sync hronized to provide i & q c a rriers w i th independent phas e of fset s f o r n u lling i out i out

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